Silicon Design for Testability (DFT) Engineer

Silicon DFT Engineer, Cloud SIlicon Minimum qualifications: Bachelor's degree in Electrical Engineering or a related field, or equivalent practical experience. 2 years of experience in Automatic Test Pattern Generation (ATPG) methods. Experience with VLSI ASIC design flows. Experience in scripting (e.g., Python, Tcl, or Perl) to automate design flows and pattern validation tasks. Preferred qualifications: Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science or a related field. 2 years of experience in the DFT flow, including implementation, scan insertion, and verification for complex ASIC/SoC designs. Experience scripting in Python or Perl or other related language. Experience with industry-standard DFT EDA tools. Ability in DFT validation, including pattern validation, Gate Level Simulations (GLS) simulation with timing, generating test cases, and debugging GLS. About the job Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide. We're the driving team behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more. Responsibilities Execute complete tasks like DFT RTL insertion, Verification, Gates DFT, Post Silicon etc within the scope of a larger project, under guidance from the manager. Select appropriate approaches from clear options to address technical challenges, under some guidance from the manager or senior team members. Implement with supervision, making steady progress without constant guidance. Experience Level Mid Level