Senior Verification Engineer

Senior Engineer (Level 1) Position: Senior Engineer (Level 1) Job Description: Principal Accountabilities • Troubleshooting errors at any stage of the process. • IP,SOC level verification using SV and/or UVM . • Assertion and coverage driven verification. • Verification of Mixed - Signal or SoC automotive ASICs. • Application of Metric - driven Verification (MDV) and / or Formal Verification methodologies - Developing and tracking of Verification plans; Integration of VIP (Verification - IP); Measure and analyze regression results. • Define block level and full-chip level test environments for server-class microprocessor-based SoC & Create test plans for unit-level and chip-level verification. • Design and implement test benches and verification environment. • Generate tests, debug failures, evaluate coverage of design. Job Complexity Job complexity may vary among jobs within this job level and will align with one of the job complexities listed below: (1) Incumbent has limited level of discretion to vary from established procedures, works under general supervision, and solves some straightforward problems. Incumbent generally has limited work experience involving basic concepts and procedures but requires formal training in theories/concepts in own function. (2) Incumbent has high level of discretion to vary from established procedures, works under broad supervision, and solves some complex problems. Incumbent generally has substantial work experience involving complex concepts and procedures in theories/concepts in own function. Location: IN-KA-Bangalore, India (eInfochips) Time Type: Full time Job Category: Engineering Services Experience Level Senior Level