Senior Formal Verification Engineer Overview We are seeking an experienced Formal Verification Engineer with 7+ years of expertise in SoC/IP verification using formal methods. The ideal candidate will drive formal verification strategy, develop scalable verification environments, create assertions and properties, perform architectural and RTL verification, and collaborate closely with architects, designers, and DV teams to ensure high-quality silicon delivery. Responsibilities Define and execute formal verification strategies for complex IPs, subsystems, and SoCs. Develop formal verification plans based on architecture and microarchitecture specifications. Create SystemVerilog Assertions (SVA), formal properties, assumptions, covers, and checkers. Debug counterexamples and work closely with designers to root-cause and resolve design issues. Drive verification closure through proof convergence, coverage analysis, and methodology improvements. Develop reusable formal verification components, libraries, and automation flows. Contribute to formal verification methodology evolution, AI-assisted verification workflows, and best practices. Mentor junior engineers and review verification plans, properties, and results. Collaborate with cross-functional teams including Architecture, RTL Design, DV, Emulation, and Silicon Validation. Qualifications Required Qualifications Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field. 7+ years of experience in semiconductor verification with significant focus on Formal Verification. Strong understanding of: Digital Design Fundamentals Computer Architecture and SoC Design Expertise in SystemVerilog and SystemVerilog Assertions (SVA). Hands-on experience with formal verification tools such as: Cadence JasperGold Synopsys VC Formal Strong debugging and analytical skills. This position will be open for a minimum of 5 days, with applications accepted on an ongoing basis until the position is filled. Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical care leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances. If you need assistance with religious accommodations and/or a reasonable accommodation due to a disability during the application process, read more about requesting accommodations. Experience Level Senior Level
Other Details
- It is a Full Time Manufacturing job for candidates with 6+ years of experience.
Who is eligible to apply for this Senior Formal Verification Engineer job at Microsoft Corporation India Private Limited?
Ans : Candidates should have All Education levels for this Senior Formal Verification Engineer job offered by Microsoft Corporation India Private Limited.
How much can you earn in this position?
Ans : Salary details will be shared during the hiring process.
What shift and timings does this job follow?
Ans : This Senior Formal Verification Engineer job follows a Day shift.
Do you need to visit the office for this job?
Ans : Yes, candidates need to visit the office and work from the location in Goraguntepalya, Bangalore.
How many openings are available for this position?
Ans : There is 1 opening available for this position.
Is this job open for all genders?
Ans : Yes, this Senior Formal Verification Engineer job is open for both male and female candidates.
Where is this job located?
Ans : This Senior Formal Verification Engineer job is located in Goraguntepalya, Bangalore.
Why should you apply for this Senior Formal Verification Engineer job?
Ans : The employer has not disclosed the salary for this role, but it is a Full Time opportunity with 1 opening available.