Senior Circuit Design Engineer - Technology and Foundry Interface

Circuit Design Engineer, Technology and Foundry Interface, Google Cloud Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 15 years of experience in process technology, circuit design, and physical design. Experience in process technology nodes, including yield and reliability, design kit, IP collaterals, and evaluating power, performance, and area. Experience in transistor level design in finfet nodes for standard cells, and memories/SRAMs, including SPICE simulations or characterization methodology. Experience with concurrent optimization across custom circuit/IP and physical design spaces. Preferred qualifications: Master's degree or PhD in Electrical Engineering. Experience with programming/scripting (Python, TCL). Proven track record of technical leadership, guiding teams through design and tapeout and interfacing with foundry suppliers. Strong understanding of semiconductor device physics and transistor characteristics. Track record of delivering circuit and physical design solutions, including across standard cells and memories/SRAMs, leading to product tapeout. Strong documentation, presentation, and communication skills. About the job Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. In this role, you will work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You will be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You will contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems. As a Circuit Design Engineer and Foundry Interface you will collaborate with our foundry partners as well as our technology, circuits, physical design, and front end teams to overcome the slowing of Moore’s Law and deliver cutting edge ASIC’s and SoC’s. You will drive competitive and reliable products by identifying the most optimal process nodes, methodologies, and IPs for our designs. You will further support on time and high quality delivery of design kits, IPs, and related collaterals to our internal teams and design flows. You will develop novel high performance computing design methodologies that co-optimize across the entire design space, then see these through from inception to maturity and tapeout. The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide. We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more. Responsibilities Lead technical evaluations of advanced process nodes and drive the strategy for custom circuits and memories/SRAMs to hit dynamic PPA targets. Engage with foundry partners to receive and debug necessary collaterals for design kits, standard cells, memories, other IPs, and more. Provide technical mentorship and guidance to circuit and physical design teams, overseeing the design and verification of custom circuits. Drive circuit level assessments of performance and power metrics. Define optimal methodologies by investigating performance, power, and area across different technology nodes and implementation techniques. Drive library cell and metal interconnect analysis and enhancements for improving PPA. Collaborate with our circuits, physical design, logic design, and technology teams in advanced CMOS nodes to ensure standard cell libraries and memories/SRAMs are seamlessly integrated. Evaluate impact due to new PDK releases. Experience Level Senior Level