Principal Physical Design Engineer

Principal Synthesis, STA Engineer About Analog Devices Analog Devices, Inc. (NASDAQ: ADI ) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, AI, and software technologies into solutions that combat climate change, reliably connect humans and the world, and help drive advancements in automation and robotics, mobility, healthcare, energy and data centers. With revenue of more than $11 billion in FY25, ADI ensures today's innovators stay Ahead of What's Possible. Learn more at www.analog.com and on LinkedIn and X . P5 Synthesis & STA Engineer About the Role As a P5 Synthesis & STA Engineer, you will provide technical leadership for Synthesis, STA, and timing closure of complex high-performance SoCs with large digital and analog interfaces. You will drive full-chip timing analysis and closure for complex, multi-GHz SoC, establish robust top-down closure methodologies, and solve complex QoR challenges spanning RTL, synthesis, constraints, clocking, and physical implementation. The role requires deep hands-on expertise combined with the ability to influence implementation strategy, introduce industry best practices, drive methodology improvements, and mentor engineers into leadership roles. Key Responsibilities Lead and own Synthesis and STA closure for complex, high-performance, multi-GHz SoCs across IP, subsystem, partition, and full-chip levels. Develop, validate, and review complex timing constraints spanning IP, subsystem, partition, and full-chip hierarchies. Drive full-chip timing signoff across multi-mode, multi-corner scenarios and establish a robust top-down timing closure methodology, driving constraints, budgets, interface timing, and convergence from full-chip to subsystem and partition levels. Demonstrate strong expertise in AOCV/SOCV methodologies, variation-aware timing analysis, and advanced-node timing signoff. Drive top-level clock planning and balancing across partitions and interfaces, working with Physical Design teams to optimize clock topology, implementation, and routing. Demonstrate strong understanding of design partitioning and hierarchical implementation, including partition boundaries, interface paths, timing budgeting, feedthrough paths, top-level clocking, and routing considerations. Root-cause complex and recurring timing convergence and QoR issues across RTL, synthesis, constraints, DFT, clocking, placement, CTS, routing, extraction, and signoff, and drive solutions to closure. Drive timing ECO strategy and execution, using both automated and manual techniques for complex setup, hold, DRC, and full-chip timing closure. Understand Scan/DFT architectures, operating modes, constraints, and associated timing implications. Drive strong automation and scalable analysis methodologies that improve productivity, debug efficiency, timing convergence, and signoff quality. Must Have Skills Experience leading multiple successful advanced-node tapeouts. Deep hands-on expertise in Digital Synthesis, STA, and timing closure for complex high-speed SoCs in advanced process technologies, preferably 16nm and below. Strong expertise in AOCV/SOCV methodologies is a must Strong expertise in developing, reviewing, scaling and debugging complex timing constraints across hierarchical designs. Proven experience owning IP, subsystem, partition, and full-chip timing convergence and signoff. Strong understanding of clock-tree analysis, clock latency/skew, clock uncertainty, clock interactions, and clock balancing. Demonstrated knowledge of design partitioning, hierarchical timing closure, top-level clock planning/balancing, interface timing, and routing considerations. Strong analytical skills to root-cause complex timing and QoR problems across different stages of design implementation and drive effective solutions. Strong expertise in automated and manual timing ECO techniques for setup, hold, DRC, and overall timing closure. Experience with leakage and dynamic power optimization as part of synthesis and implementation. Strong understanding of the complete RTL-to-GDS flow, including floorplanning, placement, CTS, routing, extraction, physical verification, EM/IR, and signoff. Strong automation mindset and demonstrated ability to develop scalable solutions for analysis, debug, convergence, and productivity improvements. Preferred Education and Experience Bachelor's or Master's degree in Electrical Engineering, Computer Engineering. 10-15 years of relevant experience. Why You'll Love Working Here At Analog Devices, you'll be part of a collaborative and innovative team that's shaping the future of technology. We offer a supportive environment focused on professional growth, competitive compensation and benefits, work-life balance, and the opportunity to work on cutting-edge projects that make a real impact on the world. Your expertise will shape the future of technology, and you’ll be supported by a culture that values continuous advancement and professional growth. Join us and help create the technologies that bridge the physical and digital worlds, making a tangible difference in how people live, work, and connect For positions requiring access to technical data, Analog Devices, Inc. may have to obtain export licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls. As such, applicants for this position – except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) – may have to go through an export licensing review process. Analog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group. Job Req Type: Experienced Required Travel: Yes, 10% of the time Shift Type: 1st Shift/Days Experience Level Senior Level