Principal Engineer, ASIC Development Engineering (RTL Design) Company Description Sandisk understands how people and businesses consume data and we relentlessly innovate to deliver solutions that enable today’s needs and tomorrow’s next big ideas. With a rich history of groundbreaking innovations in Flash and advanced memory technologies, our solutions have become the beating heart of the digital world we’re living in and that we have the power to shape. Sandisk meets people and businesses at the intersection of their aspirations and the moment, enabling them to keep moving and pushing possibility forward. We do this through the balance of our powerhouse manufacturing capabilities and our industry-leading portfolio of products that are recognized globally for innovation, performance and quality. Sandisk has two facilities recognized by the World Economic Forum as part of the Global Lighthouse Network for advanced 4IR innovations. These facilities were also recognized as Sustainability Lighthouses for breakthroughs in efficient operations. With our global reach, we ensure the global supply chain has access to the Flash memory it needs to keep our world moving forward. Job Description In this role you will design and implements IPs and subsystems. Dealing the best of class IPs for all SanDisk products At hands on in IP / blocks / subsystem complex design in verilog / sysverilog Strong digital design development and execution skills , solving bugs Experience in grooming team of 1-4 engineers, interacting with many team Deep expirience in debug , solving problem, see the architecture view, proposing solutions. Working with EDA tools Deep knowledge on PCIe, axi , DMA, AHB interfaces Experience in Verification UVM , DDR , flash is a plus Qualifications BE or Master's in Electronics Engineering, Electrical Engineering, Computer Engineering, or related field 9+ years of experience in ASIC development, with a proven track record of leading complex projects Advanced knowledge of ASIC design and development, including digital design, verification methodologies, and proficiency in hardware description languages (e.g., Verilog, VHDL) Expertise in high-performance and low-power design techniques, with hands-on experience using industry-standard EDA tools Strong problem-solving, debugging, and analytical skills to resolve complex technical issues Excellent leadership, mentoring, and communication skills, with the ability to guide engineering teams and articulate complex technical concepts Understanding of semiconductor industry trends and willingness to work in Bengaluru, India, with occasional travel Additional Information Sandisk thrives on the power and potential of diversity. As a global company, we believe the most effective way to embrace the diversity of our customers and communities is to mirror it from within. We believe the fusion of various perspectives results in the best outcomes for our employees, our company, our customers, and the world around us. We are committed to an inclusive environment where every individual can thrive through a sense of belonging, respect and contribution. Sandisk is committed to offering opportunities to applicants with disabilities and ensuring all candidates can successfully navigate our careers website and our hiring process. Please contact us at jobs.accommodations@sandisk.com to advise us of your accommodation request. In your email, please include a description of the specific accommodation you are requesting as well as the job title and requisition number of the position for which you are applying. Experience Level Senior Level
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- It is a Full Time Manufacturing job for candidates with 6+ years of experience.
More about this Principal Engineer - ASIC RTL Design job
What are the eligibility criteria for this Principal Engineer - ASIC RTL Design job?
Ans : Candidates should have All Education levels with 9-7 years of experience for this Principal Engineer - ASIC RTL Design job offered by Sandisk India Device Design Centre Pvt.ltd in Chikkaballapur, Bangalore.
What salary is offered for this Principal Engineer - ASIC RTL Design job?
Ans : Salary details will be shared during the hiring process.
What shift and timings does this job follow?
Ans : This Principal Engineer - ASIC RTL Design job follows a Day shift.
Do you need to visit the office for this job?
Ans : Yes, candidates need to visit the office and work from the location in Chikkaballapur, Bangalore.
How many vacancies are there for this Principal Engineer - ASIC RTL Design job?
Ans : There is 1 vacancy for this Principal Engineer - ASIC RTL Design role.
Is this job open for all genders?
Ans : Yes, this Principal Engineer - ASIC RTL Design job is open for both male and female candidates.
What is the job location for this position?
Ans : The job location for this Principal Engineer - ASIC RTL Design position is Chikkaballapur, Bangalore.
What makes this Principal Engineer - ASIC RTL Design job a good opportunity?
Ans : The employer has not disclosed the salary for this role, but it is a Full Time opportunity with 1 opening.