Design Engineer I At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. What we are looking for : Minimum Qualifications: • 2-10 years (with Btech) or 8 years (with Mtech) experience in Post-Silicon PHY, Systems Interop and Compliance testing. • 2-3 years of management experience leading/mentoring a small team of engineers • Physical Layer and Protocol layer experience on AT LEAST ONE High speed SERDES on PCIe/CXL/UCIe/Ethernet. • Debug skills and Experience in using lab equipment such as Oscilloscopes, Bit Error Rate Testers, Protocol Exercisers, Analyzers. Preferred Qualifications: • Experience leading System testing efforts for SERDES solutions. • Experience in PCIe/UCIe LTSSM states is a plus. • 1-2 years of experience in FPGA Design and Schematic design. • 1-2 years of IP/SoC Physical Layer Electrical Validation experience is a plus. • Familiarity with Verilog RTL coding for FPGA, python,C/C++ • Good communication skills We’re doing work that matters. Help us solve what others can’t. Experience Level Senior Level
Other Details
It is a Full Time Manufacturing job for candidates with 2 - 6+ years Experience.
More about this Design Engineer - Physical Layer and System Testing job
Who is eligible to apply for this Design Engineer - Physical Layer and System Testing job at Cadence Design Systems India Private Limited?
Ans : Candidates should have All Education levels for this Design Engineer - Physical Layer and System Testing job offered by Cadence Design Systems India Private Limited.
How much can you earn in this position?
Ans : Salary details will be shared during the hiring process.
What shift and timings does this job follow?
Ans : This Design Engineer - Physical Layer and System Testing job follows a Day shift.
Do you need to visit the office for this job?
Ans : Yes, candidates need to visit the office and work from the location in Nelamangala, Bangalore.
How many openings are available for this position?
Ans : There is 1 opening available for this position.
Is this job open for all genders?
Ans : Yes, this Design Engineer - Physical Layer and System Testing job is open for both male and female candidates.
Where is this job located?
Ans : This Design Engineer - Physical Layer and System Testing job is located in Nelamangala, Bangalore.
Why should you apply for this Design Engineer - Physical Layer and System Testing job?
Ans : The employer has not disclosed the salary for this role, but it is a Full Time opportunity with 1 opening available.
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Cadence Design Systems India Private Limited
Nelamangala, Bangalore
2 - 6+ years Experience in Manufacturing
Full Time
High Demand
