ASIC Design Verification Engineer

Design Verification Engineer, Silicon Engineering Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 4 years of experience verifying digital logic at RTL using System Verilog for FPGAs and ASICs. Experience with UVM Testbenches/environments. Preferred qualifications: Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture. Expertise in creating/using verification components and environments in UVM methodology at IP or Subsystem level. Experience with image processing, computer vision or machine learning IPs. Experience with AMBA(APB/AXI/ACE) or other standard protocols. Familiarity with CPU, GPU or other compute/ML architectures. Excellent communication and collaboration skills with the ability to work with cross-functional teams. About the job Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. As an ASIC Design Verification Engineer on the Silicon team, you will verify next-generation custom silicon accelerators and SoCs, build advanced Universal Verification Methodology (UVM) test environments, and collaborate across design, architecture, and emulation teams to deliver production-quality silicon. The Platforms and Devices team encompasses Google's various computing software platforms across environments (desktop, mobile, applications), as well as our first party devices and services that combine the best of Google AI, software, and hardware. Teams across this area research, design, and develop new technologies to make our user's interaction with computing faster and more seamless, building innovative experiences for our users around the world. Responsibilities Create and improve constrained-random verification environments using SystemVerilog and UVM. Use SystemVerilog Assertions (SVA) and formal tools for formal verification. Perform power-aware simulations and formal verification to validate power management features like clock gating, power gating, and Dynamic Voltage and Frequency Scaling (DVFS). Develop and implement power-aware test cases, including stress and corner-case scenarios, for robust power integrity. Develop and execute coverage-driven verification plans to ensure comprehensive coverage of ASIC designs. Collaborate with design engineers to resolve coverage issues and improve design quality. Plan the verification of complex digital design blocks by understanding design specifications and collaborating with design engineers to identify key verification scenarios. Experience Level Mid Level