Senior Design Verification Engineer

Senior Design Verification Engineer Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, or equivalent practical experience. Experience with ultra-low latency, high-density micro-display technologies. Experience transitioning UVM testbenches to hardware emulation platforms. Experience with scripting languages such as Python or Perl or Makefile. Preferred qualifications: Master's degree in Electrical Engineering, Computer Engineering, or equivalent practical experience. Experience with tools such as MicroLED, Micro-Organic Light Emitting Diode (OLED) for Augmented Reality/Virtual Reality/Extended Reality. (AR/VR XR) systems. Expertise with Palladium, Zebu and Veloce. About the job Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology. Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Responsibilities Define comprehensive verification strategies, test architectures, and detailed test plans covering full chip, subsystem, and block levels. Architect scalable SystemVerilog and Universal Verification Methodology (UVM) verification environments with constrained-random stimulus generation, protocol checkers, and automated scoreboards. Establish bit-accurate reference models using C/C++ integrated via Direct Programming Interface (DPI)-C to verify complex pixel-processing algorithms and video pipelines dynamically. Formulate metric-motivated verification methodologies, tracking functional coverage, code coverage (e.g., line, branch, toggle, expression), and assertion density. Verify high-speed protocol interfaces and link layers against industry standards, including packetization, link training, error management, and recovery mechanisms. Experience Level Senior Level