Senior Design for Test (DFT) Engineer

Senior Engineer (Level 1) Position: Senior Engineer (Level 1) Job Description: • Responsible for scan insertion and validation, IO Test IP tests, BIST, MBIST insertion and validation, ATPG and Pattern validation w/wo Timing, DFT mode timing Analysis and sign off. • Responsible for a comprehensive DFT plan. • Architect and implement solutions for Scan and built-in self-test (Memory and Logic BIST) circuitry to test devices in SoC • Partner with cross functional teams & to Coordinate all DFT activities • Provide support to close STA timing across all DFT modes for blocks and top. • Responsible for digital design automation, flow-automation & Take measures which saves time in future projects (action items in flow revision) • Ensure successful delivery of all the project deliverable to customers Job Complexity ● Manages professional employees and/or supervisors or supervises large, complex technical or business support or production operations team(s) ● Is accountable for the performance and results of a team within own discipline or function ● Adapts departmental plans and priorities to address resource and operational challenges ● Decisions are guided by policies, procedures and business plan; receives guidance from senior manager ● Provides technical guidance to employees, colleagues and/or customers ● Accountable for results of a small team ● Exercises limited management authority; sets employee performance objectives, conducts performance reviews and recommends pay actions ● Defines team operating standards and ensures essential procedures are followed based on knowledge of own discipline Location: IN-GJ-Ahmedabad, India-Aryan Bld-2 (eInfochips) Time Type: Full time Job Category: Engineering Services Experience Level Senior Level