Design Technology Co-Optimization Engineer

Design Technology Co-Optimization Engineer, Google Cloud Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 5 years of experience in Physical Design (e.g., Register-Transfer Level- to-Graphic Database System (RTL-to-GDS)) or technology development focusing on advanced nodes (e.g., 7nm, 5nm, or below). Experience with scripting and automation using Tcl, Python or Perl Preferred qualifications: Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture. Experience with Complementary Metal-Oxide-Semiconductor (CMOS) device physics, FinFET/nanosheet architectures, and the impact of layout parasitics on PPA. Experience in DTCO, including standard cell library characterization, metal stack optimization, and evaluation of scaling boosters (e.g., backside power delivery). Experience using industry standard tools for synthesis, place and route, static timing analysis, transistor level design in advanced finfet technology nodes, including SPICE simulations. Experience working with major foundry technology files (PDKs) and interpreting Design Rule Manuals (DRM) to guide physical implementation. About the job Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. As a Design Technology Co-Optimization (DTCO) Engineer, you will bridge the gap between process technology and product architecture to define the next generation of data center-class silicon. You will be responsible for extracting maximum process entitlement by evaluating advanced logic nodes and emerging transistor architectures. You will conduct rigorous Place and Route (P and R) experiments and sensitivity analysis to influence standard cell library architecture, metal stack definitions, and design rules. You will collaborate deeply with Foundry, Internet Protocol (IP), and Architecture teams to identify Power, Performance, and Area (PPA) bottlenecks and drive System Technology Co-Optimization (STCO) initiatives. You will involve performing high-fidelity physical implementation sweeps, analyzing the impact of scaling boosters, and developing automated methodologies to quantify PPA gains. You will ensure Google’s hardware achieves efficiency and power density. The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide. We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more. Responsibilities Execute high-fidelity Place and Route (P and R) experiments to evaluate the PPA impact of advanced process features, library architectures, and design rule variations on data center-class IP. Drive Design Technology Co-Optimization (DTCO) by collaborating with foundries and internal technology teams to define optimal metal stacks, track heights, and scaling boosters (e.g., backside power delivery, buried power rails). Quantify process entitlement through systematic benchmarking of logic and memory macros, identifying bottlenecks in power density and timing closure for next-generation nodes. Develop automated physical design methodologies and flows to accelerate technology pathfinding and enable rapid "what-if" analysis of emerging transistor architectures. Influence System Technology Co-Optimization (STCO) by partnering with Hardware Architects and Circuit Designers to translate process-level innovations into system-level performance gains. Experience Level Mid Level