ASIC Design for Testability Engineer

ASIC Design for Testability Engineer, Silicon Minimum qualifications: Bachelor's degree in Building Engineering, Electrical and Electronics Engineering, Controls, IT, or equivalent practical experience. 4 years of experience in DFT/DFD flows and methodologies. Experience with Scan insertion, Automatic Test Pattern Generation (ATPG), Gate Level Simulations and Silicon Debug, Low Power designs, Built-In Self-Test (BIST), Joint Test Action Group (JTAG), Internal JTAG (IJTAG) tools and flow. Experience with DFT EDA Tool Tessent/Genus/FC/Simvision etc. Preferred qualifications: Experience with DFT for a Complex subsystem with multiple physical partitions. Experience with IJTAG ICL, PDL terminology, ICL extraction, ICL modeling with Siemens Tessent Tool. Experience with Spyglass-DFT, and DFT Scan constraints and evaluating DFT STA paths. Experience with a scripting language such as Perl or Python. Knowledge of high performance design DFT techniques like SSN, HighBandwidth IJTAG. About the job Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology. Responsibilities Work with a team of DFT engineers, working with RTL, Physical Designer Engineers, SOC DFT and Product Engineering team. Work on Subsystem level DFT SCAN, MBIST Architecture with multiple voltage, power domains. Write basic to complex scripts to automate the DFT flow. Develop tests that can be used for Production in the ATE flow. Work with the members of the DFT team to deliver overall deliverables for 2 or more complex Subsystems in a SoC. Experience Level Mid Level