Senior Silicon Validation and Hardware Debug Engineer

Member Technical Staff (Level 2) Position: Member Technical Staff (Level 2) Job Description: What You'll Be Doing Principal Accountabilities: Lead pre & post-silicon functional validation activities for complex SoCs, MCUs, and ASICs. Drive board bring-up covering power, reset, clock, straps, fuses, hardware initialization, and JTAG debug. Develop and execute validation plans, test cases, and debug strategies for functional and system-level validation. Lead hardware debug and failure analysis by performing root cause investigations of boot failures, system hangs, data corruption, memory access issues, and intermittent hardware failures. Validate and debug interfaces such as PCIe, Ethernet, CAN/CAN FD, LIN, FlexRay, UART, I2C, and SPI. Perform Lab Validation & debugging using oscilloscopes, logic analyzers, protocol analyzers, bus sniffers, and JTAG. Validate SRAM/Flash and debug memory initialization, access, and data integrity issues. Read schematics and perform pin-level signal tracing to isolate hardware issues. Work with RTL/design, firmware, architecture, and system teams to identify root causes and drive issues to closure. Lead technical debug activities and mentor validation engineers. Job Complexity: Leads technical execution of silicon validation and hardware debug activities. Provides technical guidance on silicon bring-up, validation, failure analysis, and debug methodologies. Review validation plans, test methodologies, and debug approaches. Coordinates with cross-functional teams to resolve complex silicon and system-level issues. Drive issue tracking, validation metrics, and closure activities. Mentor junior engineers on silicon debug and validation best practices. What Are We Looking For 10+ years of strong hands-on expertise in silicon bring-up, board-level debugging, protocol validation, hardware failure analysis, and lab-based validation on real silicon platforms. Strong experience with SoC, MCU, or ASIC bring-up and functional validation. Hands-on experience with power, reset, clocking, straps, configuration errors. Experience debugging PCIe, Ethernet, CAN/CAN FD, LIN, FlexRay, UART, I2C, or SPI interfaces. Strong understanding of SRAM/Flash, register-level configuration, signal integrity, and hardware failure analysis. Proficiency with oscilloscopes, logic analyzers, protocol analyzers, and other hardware debug equipment. Ability to read schematics and perform pin-level signal tracing. Strong root-cause analysis and problem-solving skills. Experience leading technical debug activities and mentoring engineers. Education B.E./B.Tech/M.E./M.Tech in Electronics, Electrical Engineering, Embedded Systems, Computer Engineering, or related field. Location - Hyderabad EXP : 15+ Years Location: IN-TG-Hyderabad, India-Gowra Palladium (eInfochips) Time Type: Full time Job Category: Engineering Services Experience Level Senior Level