Sr. Principal Design Engineer At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. BTech/ MTech in Engineering 12+ years of VLSI industry experience in Verification. SOC level verification experience preferred IP or Subsystem or SOC level verification experience Should be able to develop test plans, tests Strong knowledge of SV, UVM. Should be able to create verification environment using UVM methodology Should be able to develop bus functional models, monitors, checkers and scoreboards. Should have experience in coverage driven verification closure. Strong individual contributor with good debug, problem solving skills Working knowledge of verification cycle for any complex IP/SOC for atleast one/more projects. Lead verification strategy and high quality execution part of SOCs/Chiplet based SOCs. Mentor and guide verification engineers, fostering technical excellence Strong experience on complete SOC level Verification Cycle Ability to collaborate and work seamlessly with design, architecture, and cross‑functional teams We’re doing work that matters. Help us solve what others can’t. Experience Level Senior Level
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It is a Full Time Manufacturing job for candidates with 6+ years of experience.
More about this Senior Principal Design Engineer - VLSI Verification job
Who is eligible to apply for this Senior Principal Design Engineer - VLSI Verification job at Cadence Design Systems India Private Limited?
Ans : Candidates should have All Education levels for this Senior Principal Design Engineer - VLSI Verification job offered by Cadence Design Systems India Private Limited.
How much can you earn in this position?
Ans : Salary details will be shared during the hiring process.
What shift and timings does this job follow?
Ans : This Senior Principal Design Engineer - VLSI Verification job follows a Day shift.
Do you need to visit the office for this job?
Ans : Yes, candidates need to visit the office and work from the location in Gandimaisamma, Hyderabad.
How many vacancies are there for this Senior Principal Design Engineer - VLSI Verification job?
Ans : There is 1 vacancy for this Senior Principal Design Engineer - VLSI Verification role.
Is this job open for all genders?
Ans : Yes, this Senior Principal Design Engineer - VLSI Verification job is open for both male and female candidates.
What is the job location for this position?
Ans : The job location for this Senior Principal Design Engineer - VLSI Verification position is Gandimaisamma, Hyderabad.
What makes this Senior Principal Design Engineer - VLSI Verification job a good opportunity?
Ans : The employer has not disclosed the salary for this role, but it is a Full Time opportunity with 1 opening.
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Cadence Design Systems India Private Limited
Gandimaisamma, Hyderabad
12 - 6+ years Experience in Manufacturing
Full Time
