Senior Engineer (Level 1) Position: Senior Engineer (Level 1) Job Description: • Incumbent will be responsible for Scan insertion and validation, BIST, MBIST insertion and validation, ATPG, IP tests and Pattern Validation w/wo Timing, DFT mode timing Analysis and sign off. • Be responsible for a comprehensive DFT plan and drive the implementation • Work with DFT and cross functional teams Location: IN-TG-Hyderabad, India-Gowra Palladium (eInfochips) Time Type: Full time Job Category: Engineering Services Experience Level Senior Level
Other Details
It is a Full Time Manufacturing job for candidates with 5 - 6+ years Experience.
More about this Senior Design for Test (DFT) Engineer job
What qualifications and experience are required for this Senior Design for Test (DFT) Engineer position?
Ans : Candidates should have All Education levels with 5-7 years of experience.
What is the salary and job type for this role?
Ans : Salary details will be shared during the hiring process.
What shift and timings does this job follow?
Ans : This Senior Design for Test (DFT) Engineer job follows a Day shift.
Do you need to visit the office for this job?
Ans : Yes, candidates need to visit the office and work from the location in Ramoji Film city, Hyderabad.
How many vacancies are there for this Senior Design for Test (DFT) Engineer job?
Ans : There is 1 vacancy for this Senior Design for Test (DFT) Engineer role.
Is this job open for all genders?
Ans : Yes, this Senior Design for Test (DFT) Engineer job is open for both male and female candidates.
What is the job location for this position?
Ans : The job location for this Senior Design for Test (DFT) Engineer position is Ramoji Film city, Hyderabad.
What makes this Senior Design for Test (DFT) Engineer job a good opportunity?
Ans : The employer has not disclosed the salary for this role, but it is a Full Time opportunity with 1 opening.