Senior Engineer (level 2) Position: Senior Engineer (level 2) Job Description: Technical: 8+ years of hands-on experience in defining DFT architecture and setting-up DFT flow, Scan insertion, MBIST insertion and Boundary Scan implementation at Fullchip level ATPG and Pattern verification at Fullchip level Implement and debug iJTAG and IEEE 1500 core wrapper-based architecture Create DFT modes timing constraints Pattern diagnosis and debug the ATE pattern failures Very good debugging skills Scripting for flow automation Should have worked on below Tools: Synopsys tools: DFTMAX, TetraMAX, VCS, Verdi and PT OR Cadence tools: Genus and Modus, NC-SIM/Irun, Sim-Vision, LEC OR Mentor Graphics tools: Tessent tool chain, TestKompress, Questa Familiarity with ATE and LBIST will be plus Location: IN-TG-Hyderabad, India-Gowra Palladium (eInfochips) Time Type: Full time Job Category: Engineering Services Experience Level Senior Level
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It is a Full Time Manufacturing job for candidates with 6+ years of experience.
More about this Senior Design for Test (DFT) Engineer job
Who is eligible to apply for this Senior Design for Test (DFT) Engineer job at Arrow Electronics India Private Limited?
Ans : Candidates should have All Education levels for this Senior Design for Test (DFT) Engineer job offered by Arrow Electronics India Private Limited.
How much can you earn in this position?
Ans : Salary details will be shared during the hiring process.
What shift and timings does this job follow?
Ans : This Senior Design for Test (DFT) Engineer job follows a Day shift.
Do you need to visit the office for this job?
Ans : Yes, candidates need to visit the office and work from the location in Rajiv Gandhi International Airport, Hyderabad.
How many vacancies are there for this Senior Design for Test (DFT) Engineer job?
Ans : There is 1 vacancy for this Senior Design for Test (DFT) Engineer role.
Is this job open for all genders?
Ans : Yes, this Senior Design for Test (DFT) Engineer job is open for both male and female candidates.
What is the job location for this position?
Ans : The job location for this Senior Design for Test (DFT) Engineer position is Rajiv Gandhi International Airport, Hyderabad.
What makes this Senior Design for Test (DFT) Engineer job a good opportunity?
Ans : The employer has not disclosed the salary for this role, but it is a Full Time opportunity with 1 opening.