Senior Engineer (Level 1) Position: Senior Engineer (Level 1) Job Description: • Responsible for scan insertion and validation, IO Test IP tests, BIST, MBIST insertion and validation, ATPG and Pattern validation w/wo Timing, DFT mode timing Analysis and sign off. • Responsible for a comprehensive DFT plan. • Architect and implement solutions for Scan and built-in self-test (Memory and Logic BIST) circuitry to test devices in SoC • Partner with cross functional teams & to Coordinate all DFT activities • Provide support to close STA timing across all DFT modes for blocks and top. • Responsible for digital design automation, flow-automation & Take measures which saves time in future projects (action items in flow revision) • Ensure successful delivery of all the project deliverable to customers Job Complexity ● Manages professional employees and/or supervisors or supervises large, complex technical or business support or production operations team(s) ● Is accountable for the performance and results of a team within own discipline or function ● Adapts departmental plans and priorities to address resource and operational challenges ● Decisions are guided by policies, procedures and business plan; receives guidance from senior manager ● Provides technical guidance to employees, colleagues and/or customers ● Accountable for results of a small team ● Exercises limited management authority; sets employee performance objectives, conducts performance reviews and recommends pay actions ● Defines team operating standards and ensures essential procedures are followed based on knowledge of own discipline Location: IN-GJ-Ahmedabad, India-Aryan Bld-2 (eInfochips) Time Type: Full time Job Category: Engineering Services Experience Level Senior Level
Other Details
It is a Full Time Manufacturing job for candidates with 5 - 6+ years Experience.
More about this Senior Design for Test (DFT) Engineer job
What qualifications and experience are required for this Senior Design for Test (DFT) Engineer position?
Ans : Candidates should have All Education levels with 5-7 years of experience.
What is the salary and job type for this role?
Ans : Salary details will be shared during the hiring process.
What shift and timings does this job follow?
Ans : This Senior Design for Test (DFT) Engineer job follows a Day shift.
Do you need to visit the office for this job?
Ans : Yes, candidates need to visit the office and work from the location in Kuber Nagar, Ahmedabad.
How many vacancies are there for this Senior Design for Test (DFT) Engineer job?
Ans : There is 1 vacancy for this Senior Design for Test (DFT) Engineer role.
Is this job open for all genders?
Ans : Yes, this Senior Design for Test (DFT) Engineer job is open for both male and female candidates.
What is the job location for this position?
Ans : The job location for this Senior Design for Test (DFT) Engineer position is Kuber Nagar, Ahmedabad.
What makes this Senior Design for Test (DFT) Engineer job a good opportunity?
Ans : The employer has not disclosed the salary for this role, but it is a Full Time opportunity with 1 opening.