Physical Design Engineer

Senior Engineer (Level 1) Position: Senior Engineer (Level 1) Job Description: Work with multi-functional teams to implement designs in test access mechanisms, IO BIST, memory BIST, scan insertion and ATPG, IP Tests. • Develop methodologies to verify DFT features in complex IP's/Sub-systems/SOC's. • Collaborate to drive test coverage driven ATPG closure and DFT signoff. Job Complexity Job complexity may vary among jobs within this job level and will align with one of the job complexities listed below: (1) Incumbent has limited level of discretion to vary from established procedures, works under general supervision, and solves some straightforward problems. Incumbent generally has limited work experience involving basic concepts and procedures but requires formal training in theories/concepts in own function. (2) Incumbent has high level of discretion to vary from established procedures, works under broad supervision, and solves some complex problems. Incumbent generally has substantial work experience involving complex concepts and procedures in theories/concepts in own function. Location: IN-TG-Hyderabad, India-Gowra Palladium (eInfochips) Time Type: Full time Job Category: Engineering Services Experience Level Senior Level