Design Engineer II At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Role Overview: Key Responsibilities: Verification Infrastructure: Simulation testbenches in C/C++/RTL and lead the development of reusable UVM environments. Advanced Verification: Champion the integration of formal verification, and AI-driven coverage analysis. Cross-Functional Collaboration: Partner with microarchitecture, RTL design, and software teams to align verification plans with ISA requirements. Required Qualifications: B.Tech/M.Tech in ECE with Experience in SystemVerilog/UVM and C/C++ for architectural modeling. Experience with processor integration (e.g., RISC-V or ARM) and industry-standard protocols like AMBA/PCIe. Expertise in scripting (Perl, Python, or Tcl) for verification flow automation. Proven track record in verifying complex pipelines, memory subsystems, or ISA implementations. We’re doing work that matters. Help us solve what others can’t. Experience Level Mid Level
Other Details
It is a Full Time Manufacturing job for candidates with 2 - 6+ years Experience.
More about this Design Verification Engineer job
Who is eligible to apply for this Design Verification Engineer job at Cadence Design Systems India Private Limited?
Ans : Candidates should have All Education levels for this Design Verification Engineer job offered by Cadence Design Systems India Private Limited.
How much can you earn in this position?
Ans : Salary details will be shared during the hiring process.
What shift and timings does this job follow?
Ans : This Design Verification Engineer job follows a Day shift.
Do you need to visit the office for this job?
Ans : Yes, candidates need to visit the office and work from the location in Sector 18 Noida, Noida.
How many openings are available for this position?
Ans : There is 1 opening available for this position.
Is this job open for all genders?
Ans : Yes, this Design Verification Engineer job is open for both male and female candidates.
Where is this job located?
Ans : This Design Verification Engineer job is located in Sector 18 Noida, Noida.
Why should you apply for this Design Verification Engineer job?
Ans : The employer has not disclosed the salary for this role, but it is a Full Time opportunity with 1 opening available.
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Cadence Design Systems India Private Limited
Sector 18 Noida, Noida
2 - 6+ years Experience in Manufacturing
Full Time
